DDR3 UDIMM Manatua Faʻaliga Faʻapitoa Faʻamatalaga

MT/s

tRCD(ns)

tRP(ns)

tRC(ns)

CL-tRCD-tRP

DDR3-1600

13.125

13.125

48.125

2011/11/11

Configuration

Refresh count

Row address

Device bank address

Device configuration

Column Address

Module rank address

4GB

8K

32K A[14:0]

8 BA[2:0]

2Gb (256 Meg x 8)

1K A[9:0]

2 S#[1:0]

Symbol

Type

Description

Ax

Input

Address inputs: Provide the row address  for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments table for density-specific
addressing information.

BAx

Input

Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.

CKx,
CKx#

Input

Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx

Input

Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DRAM.

DMx

Input

Data mask (x8 devices only): DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write access.
Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.

ODTx

Input

On-die  termination:  Enables  (registered  HIGH)  and  disables  (registered  LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.

Par_In

Input

Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#,
CAS#,
WE#

Input

Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.

RESET#

Input
(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and
the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as
though a normal power-up was executed.

Sx#

Input

Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.

SAx

Input

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address
range on the I2C bus.

SCL

Input

Serial
communication to and from the temperature sensor/SPD EEPROM on the I2C bus.

CBx

I/O

Check bits: Used for system error detection and correction.

DQx

I/O

Data input/output: Bidirectional data bus.

DQSx,
DQSx#

I/O

Data strobe: Differential data strobes. Output with read data; edge-aligned with read data;
input with write data; center-alig

SDA

I/O

Serial
sensor/SPD EEPROM on the I2C bus.

TDQSx,
TDQSx#

Output

Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no
function.

Err_Out#

Output (open
drain)

Parity error output: Parity error found on the command and address bus.

EVENT#

Output (open
drain)

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.

VDD

Supply

Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD.

VDDSPD

Supply

Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.

VREFCA

Supply

Reference voltage: Control, command, and address VDD/2.

VREFDQ

Supply

Reference voltage: DQ, DM VDD/2.

VSS

Supply

Ground.

VTT

Supply

Termination voltage: Used for control, command, and address VDD/2.

NC

–

No connect: These pins are not connected on the module.

NF

–

No function: These pins are connected within the module, but provide no functionality.